Modern integrated circuits are designed using programmed computers. Such computers are conventionally programmed with Electronic Design Automation (EDA) and Electronic Computer-Aided Design (ECAD) tools (generally referred to as EDA tools). EDA tools process an abstract representation of a circuit design into a physical representation of the circuit design that can be implemented using integrated circuitry. For example, a circuit design may be specified by a designer using a hardware description language (HDL), such as the very high speed integrated circuit hardware description language (VHDL) or VERILOG. Notably, a model of the circuit design is typically simulated prior to physical implementation in order to ascertain the functional correctness of the design and/or obtain various performance estimates. EDA simulators typically produce quantitative data that characterizes the circuit design.
Conventional EDA systems cannot map ordinary sequential programs into efficient concurrent circuit implementations. Sequential programming languages, such as C, obscure the concurrency available in an algorithm and encourage the specification of systems that assume all data resides in one globally accessible memory. As such, this form of specification is not suited for concurrent circuit implementations. Present EDA simulators are configured to process sequential descriptions of an algorithm or system. Thus, such EDA simulators disregard metrics that quantify the amount of potential parallelism in a concurrent circuit implementation. Accordingly, there exists a need in the art for a method and apparatus for obtaining quantitative data characterizing a concurrent circuit design.